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2020 – today
- 2020
[c11]Ákos Zarándy, Péter Földesy, Ádám Nagy, Imre Jánoki
, Dániel Terbe, Máté Siket, Miklós Szabó, Judit Varga:
Multi-Level Optimization for Enabling Life Critical Visual Inspections of Infants in Resource Limited Environment. ISCAS 2020: 1-5- [i1]Péter Földesy, Imre Jánoki, Ákos Zarándy, Péter Pázmány:
Non-Contact Vital-Sign Monitoring System for Premature Infants in Neonatal Intensive Care Units. ERCIM News 2020(122) (2020)
2010 – 2019
- 2013
- [j7]Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Alberto Rodríguez-Pérez, Carlos M. Domínguez-Matas, Jorge Fernández-Berni, Gustavo Liñán Cembrano, Maria Belen Pérez-Verdú, Zoltán Kárász, Manuel Suárez-Cambre, Víctor Manuel Brea Sánchez, Tamás Roska, Ángel Rodríguez-Vázquez:
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips. J. Syst. Archit. 59(10-A): 908-919 (2013) - 2012
- [c10]Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi:
Test and configuration architecture of a sub-THz CMOS detector array. DDECS 2012: 101-104 - [c9]Péter Földesy:
Characterization of silicon field effect transistor sub-THz detectors for imaging systems. ISCAS 2012: 934-937
2000 – 2009
- 2009
- [c8]Péter Földesy, Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Ángel Rodríguez-Vázquez, Tamás Roska:
3D multi-layer vision architecture for surveillance and reconnaissance applications. ECCTD 2009: 185-188 - 2008
- [j6]Péter Földesy, Ákos Zarándy, Csaba Rekeczky:
Configurable 3D-integrated focal-plane cellular sensor-processor array architecture. Int. J. Circuit Theory Appl. 36(5-6): 573-588 (2008) - 2007
- [c7]Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska:
3D integrated scalable focal-plane processor array. ECCTD 2007: 954-957 - [c6]Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska:
High performance processor array for image processing. ISCAS 2007: 1177-1180 - 2006
- [j5]Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska:
Digital implementation of cellular sensor-computers. Int. J. Circuit Theory Appl. 34(4): 409-428 (2006) - 2005
- [c5]Ákos Zarándy, Péter Földesy, Tamás Roska:
Per-pixel integration time controlled image sensor. ECCTD 2005: 149-152 - [c4]Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska:
Various implementations of topographic, sensory, cellular wave computers. ISCAS (6) 2005: 5802-5805 - 2003
- [j4]György Cserey, Csaba Rekeczky, Péter Földesy:
PDE-Based Histogram Modification With Embedded Morphological Processing Of The Level-Sets. J. Circuits Syst. Comput. 12(4): 519-538 (2003) - [j3]Ákos Zarándy, Csaba Rekeczky, Péter Földesy, István Szatmári:
The New Framework Of Applications: The Aladdin System. J. Circuits Syst. Comput. 12(6): 769-781 (2003) - 2002
- [j2]Péter Földesy, Ángel Rodríguez-Vázquez:
A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips. Int. J. Circuit Theory Appl. 30(2-3): 139-163 (2002) - 2001
- [c3]Csaba Rekeczky, István Szatmári, Péter Földesy:
Computing on silicon with trigger waves: experiments on CNN-UM chips. ISCAS (3) 2001: 49-52 - 2000
- [c2]István Szatmári, Ákos Zarándy, Péter Földesy, László Kék:
An analogic CNN engine board with the 64×64 analog I/O CNN-UM chip. ISCAS 2000: 124-127 - [c1]Gustavo Liñán, Péter Földesy, A. Rodrignez-Vazquez, Servando Espejo, Rafael Domínguez-Castro:
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip. ISCAS 2000: 401-404
1990 – 1999
- 1997
- [j1]Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska:
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage. IEEE J. Solid State Circuits 32(7): 1013-1026 (1997)
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