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2020 – today
- 2022
[c7]Benjamin Prautsch, Thomas Markwirth, Frank Schenkel, Reimund Wittmann, Uwe Eichler
, Jens Lienig:
A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models. SMACD 2022: 1-4
2000 – 2009
- 2003
- [c6]Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD 2003: 241-246 - 2002
- [c5]Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb:
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE 2002: 581-585 - 2001
- [c4]Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich:
A fast method for identifying matching-relevant transistor pairs. CICC 2001: 361-364 - [c3]Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich:
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC 2001: 858-863 - 2000
- [c2]Kurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala:
WiCkeD: analog circuit synthesis incorporating mismatch. CICC 2000: 511-514 - [c1]Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich:
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE 2000: 42-47
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