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ORCIDKonstantinos Manolopoulos
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Journal Articles
- 2016
[j3]Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras:
An efficient multiple precision floating-point Multiply-Add Fused unit. Microelectron. J. 49: 10-18 (2016)- 2010
- [j2]Konstantinos Babionitakis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos:
Fully Systolic FFT Architecture for Giga-sample Applications. J. Signal Process. Syst. 58(3): 281-299 (2010) - 2008
- [j1]Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos:
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. 41(1): 135-152 (2008)
Conference and Workshop Papers
- 2017
- [c7]Robin Aggleton, Luis E. Ardila-Perez
, Fionn Amhairghen Ball, Matthias Norbert Balzer, James John Brooke, Luigi Calligaris, Michele Caselle, Davide Cieri, Emyr John Clement, Geoffrey Hall, Kristian Harder, Peter R. Hobson, Gregory M. Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander D. Morton, David Newbold, Sudarshan Paramesvaran, Mark Franco Pesaresi, Ivan D. Reid, Andrew W. Rose, Oliver Sander, Thomas Schuh, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Sioni Paris Summers, Alexander D. Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis, Marc Weber:
A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN. FPL 2017: 1-4 - 2012
- [c6]Konstantinos Manolopoulos, A. Belias, Georgios Georgis, Dionysios I. Reisis, E. G. Anasontzis:
Signal processing for deep-sea observatories with reconfigurable hardware. ICECS 2012: 81-84 - 2011
- [c5]Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras:
An efficient multiple precision floating-point multiplier. ICECS 2011: 153-156 - 2010
- [c4]Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras:
An efficient dual-mode floating-point Multiply-Add Fused Unit. ICECS 2010: 5-8 - 2009
- [c3]Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis:
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. SoCC 2009: 93-96 - 2007
- [c2]Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras:
High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures. ICECS 2007: 146-149 - 2006
- [c1]Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras:
A High Performance VLSI FFT Architecture. ICECS 2006: 810-813
Coauthor Index
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