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Journal Articles
- 2010
[j7]Tameesh Suri, Aneesh Aggarwal:
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration. Int. J. Parallel Program. 38(3-4): 203-224 (2010)- 2009
- [j6]Aneesh Aggarwal:
Complexity Effective Bypass Networks. Trans. High Perform. Embed. Archit. Compil. 2: 201-221 (2009) - 2008
- [j5]Prateek Pujara, Aneesh Aggarwal:
Cache Noise Prediction. IEEE Trans. Computers 57(10): 1372-1386 (2008) - 2007
- [j4]Aneesh Aggarwal, Pradip Bose, Mohamed Zahran:
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop. SIGARCH Comput. Archit. News 35(3): 1 (2007) - 2005
- [j3]Aneesh Aggarwal, Manoj Franklin:
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency. IEEE Trans. Computers 54(12): 1496-1507 (2005) - [j2]Aneesh Aggarwal, Manoj Franklin:
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. IEEE Trans. Parallel Distributed Syst. 16(10): 944-955 (2005) - 2004
- [j1]Abdel-Hameed A. Badawy, Aneesh Aggarwal, Donald Yeung, Chau-Wen Tseng:
The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems. J. Instr. Level Parallelism 6 (2004)
Conference and Workshop Papers
- 2017
- [c29]Tameesh Suri, Aneesh Aggarwal:
Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. ARCS 2017: 99-110 - 2009
- [c28]Tameesh Suri, Aneesh Aggarwal:
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. Conf. Computing Frontiers 2009: 151-160 - [c27]Saugata Ghose, Latoya Gilgeous, Polina Dudnik, Aneesh Aggarwal, Corey Waxman:
Architectural support for low overhead detection of memory violations. DATE 2009: 652-657 - [c26]Tameesh Suri, Aneesh Aggarwal:
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. VLSI Design 2009: 145-150 - [c25]Sandeep Sirsi, Aneesh Aggarwal:
Exploring the Limits of Port Reduction in Centralized Register Files. VLSI Design 2009: 535-540 - 2008
- [c24]Tameesh Suri, Aneesh Aggarwal:
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware. HiPC 2008: 365-377 - [c23]Sumeet Kumar, Aneesh Aggarwal:
Speculative instruction validation for performance-reliability trade-off. HPCA 2008: 405-414 - [c22]Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal:
Optimizing XML processing for grid applications using an emulation framework. IPDPS 2008: 1-11 - 2007
- [c21]Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal:
McGrid: framework for optimizing grid middleware on multi-core processors. SOCP@HPDC 2007: 9-16 - [c20]Prateek Pujara, Aneesh Aggarwal:
Increasing cache capacity through word filtering. ICS 2007: 222-231 - [c19]Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal:
Efficient XML-Based Grid Middleware Design for Multi-Core Processors. ICWS 2007: 1197-1198 - 2006
- [c18]Sumeet Kumar, Aneesh Aggarwal:
Self-checking instructions: reducing instruction redundancy for concurrent error detection. PACT 2006: 64-73 - [c17]Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal:
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. HiPC 2006: 135-147 - [c16]Prateek Pujara, Aneesh Aggarwal:
Increasing the cache efficiency by eliminating noise. HPCA 2006: 145-154 - [c15]Sumeet Kumar, Aneesh Aggarwal:
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. HPCA 2006: 212-221 - [c14]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal:
Address-Value Decoupling for Early Register Deallocation. ICPP 2006: 337-346 - 2005
- [c13]Prateek Pujara, Aneesh Aggarwal:
Restrictive Compression Techniques to Increase Level 1 Cache Capacity. ICCD 2005: 327-333 - [c12]Aneesh Aggarwal:
Reducing latencies of pipelined cache accesses through set prediction. ICS 2005: 2-11 - 2004
- [c11]Aneesh Aggarwal:
Single FU Bypass Networks for High Clock Rate Superscalar Processors. HiPC 2004: 319-332 - [c10]Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
:
Defining Wakeup Width for Efficient Dynamic Scheduling. ICCD 2004: 36-41 - [c9]Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal:
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors. PACS 2004: 30-45 - 2003
- [c8]Aneesh Aggarwal, Manoj Franklin:
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency. IEEE PACT 2003: 46-55 - [c7]Aneesh Aggarwal, Manoj Franklin:
Energy Efficient Asymmetrically Ported Register Files. ICCD 2003: 2-7 - 2002
- [c6]Aneesh Aggarwal, Manoj Franklin:
Hierarchical Interconnects for On-Chip Clustering. IPDPS 2002 - [c5]Aneesh Aggarwal:
Software caching vs. prefetching. MSP/ISMM 2002: 263-268 - 2001
- [c4]Aneesh Aggarwal, Manoj Franklin:
Putting Data Value Predictors to Work in Fine-Grain Parallel Processors. HiPC 2001: 204-213 - [c3]Abdel-Hameed A. Badawy, Aneesh Aggarwal, Donald Yeung, Chau-Wen Tseng:
Evaluating the impact of memory system performance on software prefetching and locality optimizations. ICS 2001: 486-500 - [c2]Aneesh Aggarwal, Manoj Franklin:
An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors. ISPASS 2001: 172-179 - [c1]Aneesh Aggarwal, Keith H. Randall:
Related Field Analysis. PLDI 2001: 214-220
Coauthor Index
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