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ORCIDYong Cheol Peter Cho
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2020 – today
- 2023
[c15]Youngsu Kwon, Jinho Han, Yong Cheol Peter Cho, Juyeob Kim, Jaehoon Chung, Jaewoong Choi, Sujin Park, Igyeong Kim, Hyunjeong Kwon, Jinkyu Kim, Hyunmi Kim, Won Jeon, Young-Deuk Jeon, Min-Hyung Cho, Minseok Choi:
Chiplet Heterogeneous-Integration AI Processor. ICEIC 2023: 1-2- 2022
- [c14]Won Jeon, Yong Cheol Peter Cho, Hyun-Mi Kim, Hyeji Kim, Jaehoon Chung, Ju-Yeob Kim, Miyoung Lee, Chun-Gi Lyuh, Jinho Han, Youngsu Kwon:
M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. AICAS 2022: 150-153 - [c13]Jinho Han, Chun-Gi Lyuh, Kyeongsun Shin, Hyun-Mi Kim, Hyunjeong Kwon, Jaehoon Chung, Yong Cheol Peter Cho, Jinkyu Kim, Jeonghui Suk, Chan Kim, Minseok Choi, Youngsu Kwon:
ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System. AICAS 2022: 466-468 - 2021
- [c12]Je-Seok Ham, Yong Cheol Peter Cho, Ju-Yeob Kim, Chun-Gi Lyuh, Jin-Kyu Kim, Jinho Han, Youngsu Kwon:
HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP. HPC Asia 2021: 139-143 - [c11]Hyeji Kim, Jaehoon Chung, Kyoung-Seon Shin, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Yong Cheol Peter Cho, Jeongmin Yang, Je-Seok Ham, Minseok Choi, Jinho Han, Youngsu Kwon:
Live Demonstration: A Neural Processor for AI Acceleration. ISCAS 2021: 1
2010 – 2019
- 2019
- [c10]Youngsu Kwon, Jeongmin Yang, Yong Cheol Peter Cho, Kyoung-Seon Shin, Jaehoon Chung, Jinho Han, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Min-Seok Choi:
Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture. AICAS 2019: 127-131 - [c9]Chan Kim, In San Jeon, Young-Su Kwon, Hyun-Mi Kim, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Min-Seok Choi:
Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. ICCE-Berlin 2019: 242-247 - [c8]Youngsu Kwon, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung-Seon Shin, Jinho Han, Chan Kim, Chun-Gi Lyuh, Hyun-Mi Kim, In San Jeon, Min-Seok Choi:
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. ISOCC 2019: 174-175 - 2017
- [c7]Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, Hoi-Jun Yoo:
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. A-SSCC 2017: 313-316 - [c6]Chan Kim, Yong Cheol Peter Cho, Youngsu Kwon:
A deep learning convolution architecture for simple embedded applications. ICCE-Berlin 2017: 74-78 - 2014
- [j1]Yong Cheol Peter Cho, Nandhini Chandramoorthy, Kevin M. Irick, Vijaykrishnan Narayanan:
Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications. J. Signal Process. Syst. 76(2): 149-168 (2014) - [c5]Siddharth Advani
, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin M. Irick, Yong Cheol Peter Cho, Jack Sampson, Vijaykrishnan Narayanan:
Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems. ICCD 2014: 501-504 - 2012
- [c4]Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan:
A reconfigurable platform for the design and verification of domain-specific accelerators. ASP-DAC 2012: 108-113 - [c3]Yong Cheol Peter Cho, Nandhini Chandramoorthy, Kevin M. Irick, Vijaykrishnan Narayanan:
Multiresolution Gabor Feature Extraction for Real Time Applications. SiPS 2012: 55-60 - 2011
- [c2]Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan:
An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization. FCCM 2011: 41-48 - [c1]Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan:
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. FPL 2011: 311-316
Coauthor Index
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