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2010 – 2019
- 2012
[j2]Atukem Nabina, José Luis Núñez-Yáñez:
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform. ACM Trans. Reconfigurable Technol. Syst. 5(4): 20:1-20:22 (2012)- [j1]José Luis Núñez-Yáñez
, Atukem Nabina, Eddie Hung, George Vafiadis:
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 437-448 (2012) - [c5]José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady:
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS 2012: 254-260 - 2010
- [c4]Atukem Nabina, José L. Núñez-Yáñez:
Dynamic Reconfiguration Optimisation with Streaming Data Decompression. FPL 2010: 602-607
2000 – 2009
- 2009
- [c3]José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi:
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC 2009: 308-313 - 2008
- [c2]Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez:
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. DSD 2008: 592-598 - [c1]Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez:
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. FPL 2008: 547-550
Coauthor Index
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