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1980 – 1989
- 1988
[j8]Trieu-Kien Truong, Irving S. Reed, In-Shek Hsu, Hsuen-Chyun Shyu, Howard M. Shao:
A Pipeline Design of a Fast Prime Factor DFT on a Finite Field. IEEE Trans. Computers 37(3): 266-273 (1988)- [j7]In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed:
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. IEEE Trans. Computers 37(6): 735-739 (1988) - [j6]Trieu-Kien Truong, D. Y. Pei, Irving S. Reed, Yao-Fang Chu, In-Shek Hsu:
An FPT algorithm with a modularized structure for computing 2-D cyclic convolutions. IEEE Trans. Acoust. Speech Signal Process. 36(9): 1540-1542 (1988) - 1987
- [j5]Hsuen-Chyun Shyu, Trieu-Kien Truong, Irving S. Reed, In-Shek Hsu, Jaw John Chang:
A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with fermat numbers. IEEE Trans. Acoust. Speech Signal Process. 35(7): 1076-1079 (1987) - 1986
- [j4]Irving S. Reed, Trieu-Kien Truong, Jørn M. Jensen, In-Shek Hsu:
The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes. IEEE Trans. Computers 35(9): 781-789 (1986) - [j3]Trieu-Kien Truong, Jaw John Chang, In-Shek Hsu, D. Y. Pei, Irving S. Reed:
Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems. IEEE Trans. Computers 35(11): 1008-1012 (1986) - [c3]Howard M. Shao, Trieu-Kien Truong, In-Shek Hsu, Leslie J. Deutsch, Irving S. Reed:
A single chip VLSI Reed-Solomon decoder. ICASSP 1986: 2151-2154 - 1985
- [j2]Jaw John Chang, Trieu-Kien Truong, Howard M. Shao, Irving S. Reed, In-Shek Hsu:
The VLSI design of a single chip for the multiplication of integers modulo a Fermat number. IEEE Trans. Acoust. Speech Signal Process. 33(6): 1599-1602 (1985) - [c2]Irving S. Reed, Trieu-Kien Truong, Jaw John Chang, Howard M. Shao, In-Shek Hsu:
VLSI residue multiplier modulo a Fermat number. IEEE Symposium on Computer Arithmetic 1985: 203-206 - [c1]Jaw John Chang, Trieu-Kien Truong, Howard M. Shao, Irving S. Reed, In-Shek Hsu:
The VLSI design of a single chip for the multiplication of integers modulo a fermat number. ICASSP 1985: 1388-1391 - 1984
- [j1]In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Ke Wang, Chiunn-Shyong Ye, Leslie J. Deutsch:
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm. IEEE Trans. Computers 33(10): 906-911 (1984)
Coauthor Index
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