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ORCIDTetsuya Ichikawa
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2000 – 2009
- 2007
[j3]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 160-168 (2007)- [j2]Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa:
Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 169-178 (2007) - 2005
- [c3]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
DPA Leakage Models for CMOS Logic Circuits. CHES 2005: 366-382 - 2004
- [i1]Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
Random Switching Logic: A Countermeasure against DPA based on Transition Probability. IACR Cryptol. ePrint Arch. 2004: 346 (2004) - 2002
- [j1]Kazumaro Aoki, Tetsuya Ichikawa, Masayuki Kanda, Mitsuru Matsui, Shiho Moriai, Junko Nakajima, Toshio Tokita:
The 128-Bit Block Cipher Camellia. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1): 11-24 (2002) - 2000
- [c2]Tetsuya Ichikawa, Tomomi Kasuya, Mitsuru Matsui:
Hardware Evaluation of the AES Finalists. AES Candidate Conference 2000: 279-285 - [c1]Kazumaro Aoki, Tetsuya Ichikawa, Masayuki Kanda, Mitsuru Matsui, Shiho Moriai, Junko Nakajima, Toshio Tokita:
Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis. Selected Areas in Cryptography 2000: 39-56
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