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ORCIDJofre Pallares
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2010 – 2019
- 2018
[j3]Raul Quijada
, Roger Dura, Jofre Pallares, Xavier Formatje, Salvador Hidalgo, Francisco Serra-Graells:
Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering. J. Hardw. Syst. Secur. 2(4): 322-332 (2018)- 2017
- [j2]Jordi Carrabina, Mohammad Mashayekhi, Jofre Pallares Cuxart, Lluís Terés:
Inkjet-Configurable Gate Arrays (IGA). IEEE Trans. Emerg. Top. Comput. 5(2): 238-246 (2017) - [c4]Jofre Pallares, Keith Sabine, Lluís Terés, Francisco Serra-Graells:
An academic EDA suite for the full-custom design of mixed-mode integrated circuits. ISCAS 2017: 1-4 - 2014
- [j1]Stepan Sutula, Jofre Pallares Cuxart, Javier Gonzalo-Ruiz, Francesc Xavier Munoz-Pascual, Lluís Terés, Francisco Serra-Graells:
A 25-µW All-MOS Potentiostatic Delta-Sigma ADC for Smart Electrochemical Sensors. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 671-679 (2014) - [c3]Stepan Sutula, Francesc Vila, Jofre Pallares, Keith Sabine, Lluís Terés, Francisco Serra-Graells:
Teaching mixed-mode full-custom VLSI design with gaf, SpiceOpus and Glade. EWME 2014: 43-48
2000 – 2009
- 2007
- [c2]Xavier Redondo, Jofre Pallares, Francisco Serra-Graells:
A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator. ISCAS 2007: 17-20 - 2003
- [c1]Jofre Pallares, Justo Sabadell, Francisco Serra-Graells:
Modeling all-MOS log filters and its application to Sigma-Delta modulators. ISCAS (1) 2003: 117-120
Coauthor Index
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