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ORCIDTheo J. Powell
Person information
- affiliation: Brigham Young University, Provo, Utah, USA
- affiliation: University of Illinois, Chanpaign, Illinois, USA
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Books and Theses
- 1969
[b1]Theo Jay Powell:
A Module Diagnostic Procedure for Combinational Logic. University of Illinois Urbana-Champaign, USA, 1969
Journal Articles
- 1969
- [j1]Theo Jay Powell:
A Procedure for Selecting Diagnostic Tests. IEEE Trans. Computers 18(2): 168-175 (1969)
Conference and Workshop Papers
- 2006
- [c12]Aman Kokrady, Theo J. Powell, S. Ramakrishnan:
Reducing Design Verification Cycle Time through Testbench Redundancy. VLSI Design 2006: 243-248 - 2005
- [c11]Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee:
Chasing subtle embedded RAM defects for nanometer technologies. ITC 2005: 9 - 2003
- [c10]Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application. ITC 2003: 386-392 - 2000
- [c9]Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce:
Delta Iddq for Testing Reliability. VTS 2000: 439-443 - 1997
- [c8]Theo J. Powell, Dan Cline, Francis Hii:
A 256Meg SDRAM BIST for Disturb Test Application. ITC 1997: 200-208 - 1996
- [c7]Theo J. Powell, James R. Pair, Bernard G. Carbajal III:
Correlating Defects to Functional and IDDQ Tests. ITC 1996: 501-510 - [c6]Theo J. Powell:
Consistently dominant fault model for tristate buffer nets. VTS 1996: 400-404 - 1995
- [c5]Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell:
Test Generation and Design for Test for a Large Multiprocessing DSP. ITC 1995: 149-156 - 1994
- [c4]Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry:
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]. VTS 1994: 192-196 - 1988
- [c3]Theo J. Powell, Fred Hwang, Bill Johnson:
Testability Features in the TMS370 Family of Microcomputers. ITC 1988: 153-160 - 1982
- [c2]Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell:
An Architecture for Testable VLSI Processors. ITC 1982: 484-493 - [c1]Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte:
Analysis and Simulation of Parallel Signature Analyzers. ITC 1982: 656-661
Coauthor Index
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