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Daniel Sheridan

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2000 – 2009

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2006
[b1]
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Daniel Sheridan:
Temporal logic encodings for SAT-based bounded model checking. University of Edinburgh, UK, 2006
[c8]
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  - journals/entcs/JacksonS07
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Paul B. Jackson, Daniel Sheridan:
A Compact Linear Translation for Bounded Model Checking. BMC@FLoC 2006: 17-30
2004
[c7]
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  - conf/fmcad/CimattiRS04
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Alessandro Cimatti, Marco Roveri, Daniel Sheridan:
Bounded Verification of Past LTL. FMCAD 2004: 245-259
[c6]
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Paul B. Jackson, Daniel Sheridan:
Clause Form Conversions for Boolean Circuits. SAT (Selected Papers 2004: 183-198
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Daniel Sheridan:
The Optimality of a Fast CNF Conversion and its Use with SAT. SAT 2004
[c4]
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Daniel Sheridan:
Bounded Model Checking with SNF, Alternating Automata, and Bu"chi Automata. BMC@CAV 2004: 83-101
2003
[c3]
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Daniel Sheridan:
Dynamic Step Size Adjustment in Iterative Deepening Search. CP 2003: 996
2002
[c2]
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Alan M. Frisch, Daniel Sheridan, Toby Walsh:
A Fixpoint Based Encoding for Bounded Model Checking. FMCAD 2002: 238-255
2001
[c1]
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Daniel Sheridan:
Comparing SAT Encodings for Model Checking. CP 2001: 784

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