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ORCIDNazanin Mansouri
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2000 – 2009
- 2009
[j2]Deniz Dal
, Nazanin Mansouri:
Power Optimization With Power Islands Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1025-1037 (2009)- 2008
- [c18]Youngsik Kim, Nazanin Mansouri:
Automated formal verification of scheduling with speculative code motions. ACM Great Lakes Symposium on VLSI 2008: 95-100 - [c17]Deniz Dal, Nazanin Mansouri:
Determining the Optimal Number of Islands in Power Islands Synthesis. ISVLSI 2008: 22-27 - 2007
- [c16]Deniz Dal, Nazanin Mansouri:
A high-level register optimization technique for minimizing leakage and dynamic power. ACM Great Lakes Symposium on VLSI 2007: 517-520 - [i1]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. CoRR abs/0710.4684 (2007) - 2006
- [c15]Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana:
Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits. CONIELECOMP 2006: 38 - [c14]Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk:
An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. ISCIS 2006: 267-276 - [c13]Deniz Dal, Adrian Nunez, Nazanin Mansouri:
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. ISQED 2006: 165-170 - 2005
- [c12]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263 - [c11]Youngsik Kim, Parija Sule, Nazanin Mansouri:
Exploiting PSL standard assertions in a theorem-proving-based verification environment. ACM Great Lakes Symposium on VLSI 2005: 400-403 - [c10]Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369 - [c9]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380 - [c8]Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Özcan Özturk:
Constraint-based Code mapping for heterogeneous Chip multiprocessors. SoCC 2005: 89-90 - 2004
- [c7]Anli He, Parija Sule, Youngsik Kim, Nazanin Mansouri:
Exploiting OVL standard assertions in a theorem-proving-based verification environment. Circuits, Signals, and Systems 2004: 249-254 - [c6]Shekhar Kopuri, Nazanin Mansouri:
Enhancing scheduling solutions through ant colony optimization. ISCAS (5) 2004: 257-260 - [c5]Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri:
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). ISQED 2004: 110-115 - 2003
- [c4]Suleyman Tosun, Hakduran Koc, Nazanin Mansouri:
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. VLSI 2003: 382- - 2000
- [j1]Nazanin Mansouri, Ranga Vemuri:
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. Formal Methods Syst. Des. 16(1): 59-91 (2000)
1990 – 1999
- 1999
- [c3]Nazanin Mansouri, Ranga Vemuri:
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. DATE 1999: 223- - 1998
- [c2]Nazanin Mansouri, Ranga Vemuri:
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. FMCAD 1998: 204-221 - [c1]Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri:
Automatic data path abstraction for verification of large scale designs. ICCD 1998: 192-194
Coauthor Index
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