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ORCIDMokhtar Hirech
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2010 – 2019
- 2010
[c7]Mokhtar Hirech:
Test cost and test power conflicts: EDA perspective. VTS 2010: 126
2000 – 2009
- 2008
- [j2]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low-Power Devices. J. Low Power Electron. 4(2): 127-138 (2008) - [c6]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low Power Devices. DATE 2008: 728-733 - 2005
- [j1]Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, Subramanian Chebiyam:
Power and Design for Test: A Design Automation Perspective. J. Low Power Electron. 1(1): 73-84 (2005) - 2002
- [c5]Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng:
Test-model based hierarchical DFT synthesis. ICCAD 2002: 286-293
1990 – 1999
- 1998
- [c4]Mokhtar Hirech, James Beausang, Xinli Gu:
A new approach to scan chain reordering using physical design information. ITC 1998: 348-355 - 1994
- [c3]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
Application of a redefinable symbolic simulation technique in VLSI testability design rules checking. Annual Simulation Symposium 1994: 255-261 - [c2]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. EDAC-ETC-EUROASIC 1994: 668 - [c1]Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. ISCAS 1994: 89-92
Coauthor Index
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