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ORCIDWei Jin 0004
Person information
- affiliation: Shanghai Jiao Tong University, School of Microelectronics, China
Other persons with the same name
- Wei Jin — disambiguation page
- Wei Jin 0001 — Google Inc., Mountain View, CA, USA (and 1 more)
- Wei Jin 0002
![[0000-0003-4552-5890]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-4552-5890")
— The Hong Kong Polytechnic University, Department of Electrical Engineering, Hong Kong - Wei Jin 0003 — Ningbo University, Faculty of Electrical Engineering and Computer Science, China
- Wei Jin 0005 — Jiangxi University of Finance and Economics, School of Statistics, Nanchang, China
- Wei Jin 0006 — University of North Texas, USA (and 2 more)
- Wei Jin 0007 — University of West Georgia, Carrollton, USA
- Wei Jin 0008 — Dalian University of Technology, China
- Wei Jin 0009 — Emory University, Atlanta, GA, USA (and 1 more)
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2010 – 2019
- 2017
[j4]Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing:
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. 58: 27-34 (2017)- [j3]Wei Jin, Guanghui He, Weifeng He, Zhigang Mao:
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. 59: 206-217 (2017) - [j2]Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok:
Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. IEEE J. Solid State Circuits 52(9): 2475-2487 (2017) - [j1]Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok:
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1032-1043 (2017) - [c6]Yongming Ding, Wei Jin, Guanghui He, Weifeng He:
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. ASICON 2017: 985-988 - [c5]Xuwei Jin, Wei Jin, Hao Zhang, Jianfei Jiang, Weifeng He:
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. ISCAS 2017: 1-4 - 2016
- [c4]Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok:
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC 2016: 129-132 - [c3]Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao:
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT 2016: 233-236 - 2011
- [c2]Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC 2011: 126-129 - [c1]Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC 2011: 440-443
Coauthor Index
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