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ORCIDYasuhiko Sasaki
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2000 – 2009
- 2006
[j3]Yasuhiko Sasaki, Naoki Kato, Hiroaki Nakaya:
Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications. IEEE J. Solid State Circuits 41(5): 1092-1099 (2006)- 2003
- [j2]Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. IEEE J. Solid State Circuits 38(5): 702-708 (2003) - 2000
- [c3]Yasuhiko Sasaki, Kazuo Yano:
Multi-aggressor relative window method for timing analysis including crosstalk delay degradation. CICC 2000: 495-498
1990 – 1999
- 1998
- [c2]Yasuhiko Sasaki, Kunihito Rikino, Kazuo Yano:
ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis. ASP-DAC 1998: 227-232 - [c1]Shunzo Yamashita, Naoki Katoh, Yasuhiko Sasaki, Yohei Akita, Hidetoshi Chikata, Kazuo Yano:
Hole filling: a novel delay reduction technique using selector logic. CICC 1998: 291-294 - 1996
- [j1]Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki:
Top-down pass-transistor logic design. IEEE J. Solid State Circuits 31(6): 792-803 (1996)
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