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ORCIDSubodh Kumar Singhal
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2020 – today
- 2023
[j7]Anuradha, Sujit Kumar Patel
, Subodh Kumar Singhal:
An area-delay efficient single-precision floating-point multiplier for VLSI systems. Microprocess. Microsystems 98: 104798 (2023)- 2021
- [j6]Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena:
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications. Turkish J. Electr. Eng. Comput. Sci. 29(4): 2012-2028 (2021) - 2020
- [j5]Sujit Kumar Patel, Subodh Kumar Singhal:
Area-delay and energy efficient multi-operand binary tree adder. IET Circuits Devices Syst. 14(5): 586-593 (2020) - [j4]Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena:
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29(12): 2050186:1-2050186:20 (2020)
2010 – 2019
- 2016
- [j3]Basant Kumar Mohanty, Subodh Kumar Singhal:
Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer. Circuits Syst. Signal Process. 35(8): 2958-2971 (2016) - [j2]Basant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, M. N. S. Swamy:
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integr. 54: 37-46 (2016) - [j1]Subodh Kumar Singhal, Basant Kumar Mohanty:
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic. J. Circuits Syst. Comput. 25(7): 1650073:1-1650073:19 (2016) - 2012
- [c3]Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal:
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS 2012: 1480-1483
2000 – 2009
- 2009
- [c2]Subodh Kumar Singhal, Deepak Sharma, Ram Mehar Singh Dhariwal:
Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs. CICSyN 2009: 264-267 - [c1]Deepak Sharma, Subodh Kumar Singhal, Ram Mehar Singh Dhariwal:
Design of 1.5 GHz Quasilumped Microstrip Highpass Filter. CICSyN 2009: 268-270
Coauthor Index
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