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2020 – today
- 2024
[c8]Bei-Shing Lien, Szu Lin Liu, Wei-Lin Lai, Yi-Chen Lu, Yung-Chow Peng, Kenny Cheng-Hsiang Hsieh:
3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -25°C to 125°C. ISSCC 2024: 68-70- [c7]Chu-En Hsia, Chin-Ho Chang, Yung-Shun Chen, Po-Yu Lai, Ching Lin Jen, Yung-Chow Peng, Shenggao Li:
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2019
- [c6]Yi-Wen Chen, Jaw-Juinn Horng, Chin-Ho Chang, Amit Kundu, Yung-Chow Peng, Mark Chen:
A 0.7V, 2.35% 3σ-Accuracy Bandgap Reference in 12nm CMOS. ISSCC 2019: 306-307 - 2014
- [c5]Chin-Ho Chang, Jaw-Juinn Horng, Amit Kundu, Chih-Chiang Chang, Yung-Chow Peng:
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET. A-SSCC 2014: 165-168 - [c4]Jaw-Juinn Horng, Szu-Lin Liu, Amit Kundu, Chin-Ho Chang, Chung-Hui Chen, Herman Chiang, Yung-Chow Peng:
A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologies. VLSIC 2014: 1-2 - 2012
- [j1]Wen-Shen Chou, Tzu-Chi Huang, Yu-Huei Lee, Yao-Yi Yang, Yi-Ping Su, Ke-Horng Chen
, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Kuei-Ann Wen, Ying-Chih Hsu, Yung-Chow Peng, Fu-Lung Hsueh:
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter. IEEE J. Solid State Circuits 47(7): 1568-1584 (2012) - 2011
- [c3]Tzu-Chi Huang, Wen-Shen Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Yung-Chow Peng, Fu-Lung Hsueh:
55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter. ESSCIRC 2011: 383-386 - 2010
- [c2]Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu:
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC 2010: 1-4
1990 – 1999
- 1994
- [c1]Chen-Yi Huang, Yung-Chow Peng, Chrong-Kuang Wang:
A BICMOS Limiting Amplifier for SONET OC-3. ISCAS 1994: 149-152
Coauthor Index
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