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ORCIDKarthikeyan Reddy
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2020 – today
- 2023
[c9]Karthik Reddy, Judd D. Bowman, Adam P. Beardsley, Gregory B. Taylor, Jayce Dowell, Craig Taylor:
An Optimized GPU Kernel for Real-Time Radio Imaging. HPCC/DSS/SmartCity/DependSys 2023: 523-527
2010 – 2019
- 2018
- [j7]Ziping Wang
, Xian Xue, Xingjia Li, Zhengxuan Jiang, Karthik Reddy:
Study on Attenuation Properties of Surface Wave of AE Simulation Source Based on OPCM Sensor Element. J. Sensors 2018: 6926594:1-6926594:6 (2018) - [j6]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53(3): 799-813 (2018) - 2017
- [c8]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC 2017: 1-4 - [i1]Karthik Reddy, Tejas K, Swathi C, Ashok K, Rajesh Kumar M:
High Capacity, Secure (n, n/8) Multi Secret Image Sharing Scheme with Security Key. CoRR abs/1710.09550 (2017) - 2016
- [c7]Ajinkya D. Deshmukh, Gaurav Bhosale, Swarup S. Medasani, Karthik Reddy, P. Hemantha Kumar, A. Chandrasekhar, P. Kiran Kumar, K. Vijayasagar:
Embedded Vision System for Atmospheric Turbulence Mitigation. CVPR Workshops 2016: 861-869 - 2015
- [j5]Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications. IEEE J. Solid State Circuits 50(8): 1785-1795 (2015) - [c6]Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu:
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC 2015: 256- - 2014
- [j4]Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu:
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. IEEE J. Solid State Circuits 49(4): 950-960 (2014) - [j3]Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu:
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits 49(10): 2228-2242 (2014) - [c5]Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A VCO-based current-to-digital converter for sensor applications. CICC 2014: 1-4 - [c4]Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu:
A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. VLSIC 2014: 1-2 - 2012
- [j2]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47(12): 2916-2927 (2012) - [c3]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154
2000 – 2009
- 2008
- [c2]Karthikeyan Reddy, Shanthi Pavan:
A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range. ESSCIRC 2008: 210-213 - 2007
- [j1]Karthikeyan Reddy, Shanthi Pavan:
Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(10): 2184-2194 (2007) - 2006
- [c1]Karthikeyan Reddy, Shanthi Pavan:
Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter. ISCAS 2006
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