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ORCIDSeyed Ebrahim Esmaeili
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Journal Articles
- 2013
[j4]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili:
Integrated Power and Clock Distribution Network. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1941-1945 (2013)- 2012
- [j3]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan:
Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1547-1551 (2012) - 2010
- [j2]Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan:
Skew compensation in energy recovery clock distribution networks. IET Comput. Digit. Tech. 4(1): 56-72 (2010) - [j1]Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. IET Comput. Digit. Tech. 4(6): 499-514 (2010)
Conference and Workshop Papers
- 2014
- [c8]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili:
10 GHz throughput FinFET dual-edge triggered flip-flops. CCECE 2014: 1-4 - 2012
- [c7]Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan:
Clock tree structure with reduced wire length using the matched-delay skew compensation technique. CCECE 2012: 1-4 - [c6]Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity. ICECS 2012: 292-295 - 2011
- [c5]Riadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam:
A high performance clock precharge SEU hardened flip-flop. ASICON 2011: 574-577 - 2010
- [c4]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan:
Estimating required driver strength in the resonant clock generator. APCCAS 2010: 927-930 - 2009
- [c3]Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered energy recovery DCCER flip-flop for low energy applications. ECCTD 2009: 57-60 - 2007
- [c2]Seyed Ebrahim Esmaeili, Nabil I. Khachab:
Efficiency Of Components' Region-Constrained Placement To Reduce FPGA's Dynamic Power Consumption. ICECS 2007: 857-860 - 2006
- [c1]Seyed Ebrahim Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam:
Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption. ISVLSI 2006: 416-417
Coauthor Index
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