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2010 – 2019
- 2012
[j1]Michael Katelman, Sean Keller, José Meseguer:
Rewriting semantics of production rule sets. J. Log. Algebraic Methods Program. 81(7-8): 929-956 (2012)- 2011
- [b1]Michael Katelman:
A meta-language for functional verification. University of Illinois Urbana-Champaign, USA, 2011 - [c11]Nirav Dave, Michael Katelman, Myron King, Arvind, José Meseguer:
Verification of microarchitectural refinements in rule-based systems. MEMOCODE 2011: 61-71 - 2010
- [c10]Michael Katelman, José Meseguer:
vlogsl: A Strategy Language for Simulation-Based Verification of Hardware. Haifa Verification Conference 2010: 129-145 - [c9]Patrick O'Neil Meredith, Michael Katelman, José Meseguer, Grigore Rosu:
A formal executable semantics of Verilog. MEMOCODE 2010: 179-188 - [c8]Michael Katelman, Sean Keller, José Meseguer:
Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits. WRLA 2010: 140-156 - [c7]Michael Katelman, José Meseguer:
Using the PALS Architecture to Verify a Distributed Topology Control Protocol for Wireless Multi-Hop Networks in the Presence of Node Failures. RTRTS 2010: 101-116
2000 – 2009
- 2009
- [c6]Sean Keller, Michael Katelman, Alain J. Martin:
A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits. ASYNC 2009: 65-76 - 2008
- [c5]Arvind, Nirav Dave, Michael Katelman:
Getting Formal Verification into Design Flow. FM 2008: 12-32 - [c4]Michael Katelman, José Meseguer, Jennifer C. Hou:
Redesign of the LMST Wireless Sensor Protocol through Formal Modeling and Statistical Model Checking. FMOODS 2008: 150-169 - [c3]Michael Katelman, José Meseguer, Santiago Escobar
:
Directed-Logical Testing for Functional Verification of Microprocessors. MEMOCODE 2008: 89-100 - 2006
- [c2]Sam Kamin, Baris Aktemur, Michael Katelman:
Staging static analyses for program generation. GPCE 2006: 1-10 - [c1]Michael Katelman, José Meseguer:
A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis. WRLA 2006: 47-60
Coauthor Index
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