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Ruey-Zone Huang

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1990 – 1999

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1991
[j1]
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Wen-Tsuen Chen, Jia-Shung Wang, Chia-Cheng Liu, Shi-Jinn Horng, Chang-Biau Yang, Ruey-Zone Huang, Bern-Cherng Liaw:
Design of An Integrated Parallel Processing System with Systolic VLSI Chips. J. Inf. Sci. Eng. 7(2): 217-235 (1991)

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