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Journal Articles
- 1999
[j4]Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska:
Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 282-292 (1999)- 1998
- [j3]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
, Mike Tien-Chien Lee:
Test-point insertion: scan paths through functional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 838-851 (1998) - [j2]Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 852-861 (1998) - 1997
- [j1]Chih-Chang Lin, Malgorzata Marek-Sadowska:
On designing universal logic blocks and their application to FPGA design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 519-527 (1997)
Conference and Workshop Papers
- 2024
- [c14]Chih-Chang Lin, Fang-Wu Tung, Chien-Hsiung Chen:
Exploring User Engagement with Smartwatch Health Services: A Comparative Study Between Taiwan and Singapore. HCI (17) 2024: 99-114 - 2020
- [c13]Chih-Chang Lin, Hao-Yu Liao, Fang-Wu Tung:
Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature Review. HCI (43) 2020: 90-104 - 2019
- [c12]Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin:
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. CICC 2019: 1-4 - [c11]Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh:
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET. VLSI Circuits 2019: 270- - 2014
- [c10]Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh:
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. ISSCC 2014: 144-145 - 2012
- [c9]Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh:
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. CICC 2012: 1-4 - 1998
- [c8]Peichen Pan, Chih-Chang Lin:
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. FPGA 1998: 35-42 - 1996
- [c7]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee:
Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273 - [c6]Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee:
Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC 1996: 334-339 - 1995
- [c5]Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Logic rectification and synthesis for engineering change. ASP-DAC 1995 - [c4]Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Logic Synthesis for Engineering Change. DAC 1995: 647-652 - [c3]Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533 - [c2]David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation. ICCAD 1995: 650-655 - 1994
- [c1]Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin:
Universal logic gate for FPGA design. ICCAD 1994: 164-168
Coauthor Index
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