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2020 – today
- 2023
[j5]Martti Forsell, Jussi Roivainen, Ville Leppänen
, Jesper Larsson Träff:
Realizing multioperations and multiprefixes in Thick Control Flow processors. Microprocess. Microsystems 98: 104807 (2023)- [c13]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. NorCAS 2023: 1-7 - 2022
- [j4]Martti Forsell, Sara Nikula, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Performance and programmability comparison of the thick control flow architecture and current multicore processors. J. Supercomput. 78(3): 3152-3183 (2022) - 2020
- [c12]Martti Forsell, Jussi Roivainen, Jesper Larsson Träff:
Optimizing Memory Access in TCF Processors with Compute-Update Operations. IPDPS Workshops 2020: 577-586
2010 – 2019
- 2019
- [c11]Markku Kiviranta, Ilkka Moilanen, Jussi Roivainen:
5G Radar: Scenarios, Numerology and Simulations. ICMCIS 2019: 1-6 - 2018
- [j3]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF processor architectures. Microprocess. Microsystems 63: 226-236 (2018) - [j2]Martti Forsell, Jussi Roivainen, Ville Leppänen:
REPLICA MBTAC: multithreaded dual-mode processor. J. Supercomput. 74(5): 1911-1933 (2018) - [c10]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Implementation of Multioperations in Thick Control Flow Processors. IPDPS Workshops 2018: 744-752 - 2017
- [c9]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF-aware processor architectures. NORCAS 2017: 1-6 - 2016
- [c8]Martti Forsell, Jussi Roivainen, Ville Leppänen:
The REPLICA on-chip network. NORCAS 2016: 1-6 - [c7]Martti Forsell, Jussi Roivainen, Ville Leppänen:
Outline of a Thick Control Flow Architecture. SBAC-PAD (Workshops) 2016: 1-6 - 2014
- [c6]Martti Forsell, Jussi Roivainen:
REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ACSSC 2014: 1709-1713 - [c5]Martti Forsell, Jussi Roivainen, Ville Leppänen:
Prototyping the MBTAC Processor for the REPLICA CMP. IPDPS Workshops 2014: 709-716
2000 – 2009
- 2008
- [c4]Martti Forsell, Jussi Roivainen:
Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. PDPTA 2008: 471-477 - 2006
- [c3]Yan Zhang, Jussi Roivainen, Aarne Mämmelä:
Clock-Gating in FPGAs: A Novel and Comparative Evaluation. DSD 2006: 584-590 - 2004
- [c2]Jussi Roivainen, Jukka Rautio:
IP-Block Based Integration of Very High Performance WLAN Modem. DSD 2004: 200-207 - 2002
- [c1]Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen:
Configurable Memory Organisation for Communication Applications. DSD 2002: 86-93 - 2001
- [j1]Janne Riihijärvi, Petri Mähönen, Mika J. Saaranen, Jussi Roivainen, Juha-Pekka Soininen:
Providing network connectivity for small appliances: a functionally minimized embedded Web server. IEEE Commun. Mag. 39(10): 74-79 (2001)
Coauthor Index
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