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Mariusz Wisniewski
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2020 – today
- 2024
- [i2]Mariusz Wisniewski, Loris Giulivi, Giacomo Boracchi:
SE3D: A Framework For Saliency Method Evaluation In 3D Imaging. CoRR abs/2405.14584 (2024) - [i1]Mariusz Wisniewski, Paraskevas Chatzithanos, Weisi Guo, Antonios Tsourdos:
Benchmarking Deep Reinforcement Learning for Navigation in Denied Sensor Environments. CoRR abs/2410.14616 (2024) - 2022
- [j4]Mariusz Wisniewski, Zeeshan A. Rana, Ivan Petrunin:
Drone Model Classification Using Convolutional Neural Network Trained on Synthetic Data. J. Imaging 8(8): 218 (2022) - 2021
- [j3]Stanislaw Deniziak, Mariusz Wisniewski:
DECOLib: A library of components for DECOmposition of discrete functions. SoftwareX 16: 100799 (2021)
2010 – 2019
- 2018
- [j2]Mariusz Wisniewski, Stanislaw Deniziak:
BMB synthesis of binary functions using symbolic functional decomposition for LUT-based FPGAs. J. Parallel Distributed Comput. 120: 16-22 (2018) - 2016
- [c6]Stanislaw Deniziak, Mariusz Wisniewski, Karol Wieczorek:
Synthesis of Multivalued Logical Networks for FPGA Implementations. DSD 2016: 657-660 - 2015
- [j1]Stanislaw Deniziak, Mariusz Wisniewski:
Symbolic Functional Decomposition of Multivalued Functions. J. Multiple Valued Log. Soft Comput. 24(5-6): 425-452 (2015) - 2013
- [c5]Mariusz Wisniewski, Gianluca Demartini, Apostolos Malatras, Philippe Cudré-Mauroux:
NoizCrowd: A Crowd-Based Data Gathering and Management System for Noise Level Data. MobiWIS 2013: 172-186 - 2011
- [c4]Marcin Wylot, Jigé Pont, Mariusz Wisniewski, Philippe Cudré-Mauroux:
dipLODocus[RDF] - Short and Long-Tail RDF Analytics for Massive Webs of Data. ISWC (1) 2011: 778-793
2000 – 2009
- 2009
- [c3]Stanislaw Deniziak, Mariusz Wisniewski:
A symbolic RTL synthesis for LUT-based FPGAs. DDECS 2009: 102-107 - 2008
- [c2]Stanislaw Deniziak, Mariusz Wisniewski:
An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs. DDECS 2008: 22-25 - [c1]Stanislaw Deniziak, Mariusz Wisniewski:
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. FPL 2008: 397-402
Coauthor Index
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last updated on 2024-11-28 21:26 CET by the dblp team
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