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ORCIDIgor Arsovski
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2010 – 2019
- 2018
[j5]Igor Arsovski, Akhilesh Patil
, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler:
1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. IEEE J. Solid State Circuits 53(1): 155-163 (2018)- 2017
- [c8]Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns:
12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. ISSCC 2017: 212-213 - 2013
- [j4]Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort:
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation. IEEE J. Solid State Circuits 48(4): 932-939 (2013) - [c7]Igor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch:
Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory. CICC 2013: 1-4 - [c6]Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus:
A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. ISSCC 2013: 322-323 - 2012
- [j3]Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic:
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE J. Solid State Circuits 47(1): 97-106 (2012) - [c5]Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort:
1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing. VLSIC 2012: 116-117 - 2011
- [c4]Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens:
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. ISSCC 2011: 254-256
2000 – 2009
- 2006
- [c3]Igor Arsovski, Reid Wistort:
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories. CICC 2006: 453-456 - [c2]Rahul Nadkarni, Igor Arsovski, Reid Wistort, Valerie Chickanosky:
Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories. ITC 2006: 1-9 - 2005
- [c1]Igor Arsovski, Rahul Nadkarni:
Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines. CICC 2005: 447-450 - 2003
- [j2]Igor Arsovski, Trevis Chandler, Ali Sheikholeslami:
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. IEEE J. Solid State Circuits 38(1): 155-158 (2003) - [j1]Igor Arsovski, Ali Sheikholeslami:
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. IEEE J. Solid State Circuits 38(11): 1958-1966 (2003)
Coauthor Index
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