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ORCIDNaser Sedaghati
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2010 – 2019
- 2017
[c14]Payman Behnam, Naser Sedaghati, Mahdi Nazm Bojnordi:
Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures. E2SC@SC 2017: 5:1-5:8- 2016
- [c13]Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu:
Core tunneling: Variation-aware voltage noise mitigation in GPUs. HPCA 2016: 151-162 - [c12]Renji Thomas, Naser Sedaghati, Radu Teodorescu:
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. ISPASS 2016: 79-89 - 2015
- [j2]Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan:
A model-driven blocking strategy for load balanced sparse matrix-vector multiplication on GPUs. J. Parallel Distributed Comput. 76: 3-15 (2015) - [c11]Naser Sedaghati, Te Mu, Louis-Noël Pouchet, Srinivasan Parthasarathy
, P. Sadayappan:
Automatic Selection of Sparse Matrix Representation on GPUs. ICS 2015: 99-108 - 2014
- [j1]Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, Radu Teodorescu, P. Sadayappan:
On Using the Roofline Model with Lower Bounds on Data Movement. ACM Trans. Archit. Code Optim. 11(4): 67:1-67:23 (2014) - [c10]Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan:
An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUs. ICS 2014: 273-282 - [c9]Arash Ashari, Naser Sedaghati, John Eisenlohr, Srinivasan Parthasarathy, P. Sadayappan:
Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications. SC 2014: 781-792 - 2012
- [c8]Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu:
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. HPCA 2012: 27-38 - 2011
- [c7]Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan:
StVEC: A Vector Instruction Extension for High Performance Stencil Computation. PACT 2011: 276-287
2000 – 2009
- 2008
- [c6]Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Abbas Hormati, Sied Mehdi Fakhraie:
An Efficient and Extendable Modeling Approach for VLIW DSP Processors. CSICC 2008: 267-274 - 2007
- [c5]Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Amin Farmahini Farahani, Mahmoud Mousavinezhad, Sied Mehdi Fakhraie:
Simulation of Voice Processing Applications through VLIW DSP Architectures. ICECS 2007: 291-293 - [c4]Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Sied Mehdi Fakhraie:
MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications. MASCOTS 2007: 173-178 - 2006
- [c3]Mahdi Nazm Bojnordi, Naser Sedaghati-Mokhtari, Omid Fatemi, Mahmoud Reza Hashemi:
An Efficient Self-Transposing Memory Structure for 32-bit Video Processors. APCCAS 2006: 1438-1441 - [c2]M. Nabipoor, S. A. Khodaian, Naser Sedaghati-Mokhtari, Sied Mehdi Fakhraie, Seyed Hamaidreza Jamali:
A High-Speed Low-Complexity VLSI SISO Architecture. APCCAS 2006: 1512-1515 - [c1]Nima Honarmand, M. Reza Javaheri, Naser Sedaghati-Mokhtari, Ali Afzali-Kusha:
Power efficient sequential multiplication using pre-computation. ISCAS 2006
Coauthor Index
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