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ORCIDChun-Po Huang
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- affiliation: National Cheng Kung University, Tainan City, Taiwan
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2010 – 2019
- 2018
[j6]Chung-Wei Hsu
, Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, Ya-Ting Shyu, Chih-Huei Hou, Hwa-An Tseng, Chih-Yuan Kung, Huan-Jui Hu:
A 12-b 40-MS/s Calibration-Free SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 881-890 (2018)- [c9]Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang:
A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. ISCAS 2018: 1-4 - [c8]Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, Hao-Sheng Wu:
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process. VLSI-DAT 2018: 1-4 - 2017
- [c7]Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang:
A 12-bit 40-MS/s calibration-free SAR ADC. ISCAS 2017: 1-4 - 2016
- [j5]Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang:
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1730-1743 (2016) - [j4]Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang:
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs. IEEE Trans. Instrum. Meas. 65(8): 1804-1817 (2016) - [j3]Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang:
A Systematic Design Methodology of Asynchronous SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1835-1848 (2016) - [c6]Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang:
A pipeline ADC with latched-based ring amplifiers. ISCAS 2016: 85-88 - 2015
- [c5]Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang:
A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. VLSI-DAT 2015: 1-4 - 2014
- [c4]Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang:
Low power pipelined SAR ADC with loading-free architecture. VLSI-DAT 2014: 1-4 - 2013
- [j2]Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 624-635 (2013) - 2012
- [j1]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1789-1802 (2012) - [c3]Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin:
A power-efficient sizing methodology of SAR ADCs. ISCAS 2012: 365-368 - 2011
- [c2]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC 2011: 528-533 - 2010
- [c1]Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang:
Performance-driven analog placement considering boundary constraint. DAC 2010: 292-297
Coauthor Index
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