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ORCIDChetana N. Keltcher
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2000 – 2009
- 2003
[j4]Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway:
The AMD Opteron Processor for Multiprocessor Servers. IEEE Micro 23(2): 66-76 (2003)
1990 – 1999
- 1996
- [j3]Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. 13(1): 67-75 (1996) - [c8]Chetana Nagendra, Mary Jane Irwin:
Design tradeoffs in CMOS FIR filters. ICASSP 1996: 3260-3263 - [c7]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Design tradeoffs in high speed multipliers and FIR filters. VLSI Design 1996: 29-32 - 1995
- [j2]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. 9(3): 193-209 (1995) - [c6]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Unifying carry-sum and signed-digital number representations for low power. ISLPD 1995: 15-20 - 1994
- [j1]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Power-delay characteristics of CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 377-381 (1994) - [c5]Raminder Singh Bajwa, Chetana N. Keltcher, Paul Keltcher, Mary Jane Irwin:
Rapid prototyping with programmable control paths. ASAP 1994: 69-74 - [c4]Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) 1994: 96-104 - [c3]Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens:
Digit pipelined discrete wavelet transform. ICASSP (2) 1994: 405-408 - 1993
- [c2]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Digit systolic algorithms for fine-grain architectures. ASAP 1993: 466-477 - [c1]Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
Edge detection using fine-grained parallelism in VLSI. ICASSP (1) 1993: 401-404
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