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2020 – today
- 2023
[c8]Inês Nogueira De Brito, Nuno Paulino, Blazej Nowacki, Tommy Mullane:
A Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators. PRIME 2023: 257-260
2010 – 2019
- 2017
- [j2]Blazej Nowacki, Nuno Paulino
, João Goes:
A Third-Order MASH $\Sigma \Delta $ Modulator Using Passive Integrators. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11): 2871-2883 (2017) - 2016
- [c7]Blazej Nowacki, Nuno Paulino, João Goes:
15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM. ISSCC 2016: 274-275 - 2014
- [c6]Blazej Nowacki, Nuno Paulino, João Goes:
A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling. ISCAS 2014: 1344-1347 - 2013
- [c5]Blazej Nowacki, Nuno Paulino, João Goes:
A simple 1 GHz non-overlapping two-phase clock generators for SC circuits. MIXDES 2013: 174-178 - 2012
- [c4]João L. A. de Melo, Blazej Nowacki, Nuno Paulino, João Goes:
Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions. ISCAS 2012: 301-304 - 2011
- [j1]Edinei Santin, Luís B. Oliveira, Blazej Nowacki, João Goes:
A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7): 1531-1541 (2011) - [c3]Blazej Nowacki, Nuno Paulino, João Goes:
A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS. ESSCIRC 2011: 271-274 - [c2]Blazej Nowacki, Nuno Paulino, João Goes:
A second-order switched-capacitor ΔΣ modulator using very incomplete settling. ISCAS 2011: 1367-1370 - 2010
- [c1]Edinei Santin, Luís B. Oliveira, Blazej Nowacki, João Goes:
Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs. ISCAS 2010: 1927-1930
Coauthor Index
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