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Conference and Workshop Papers
- 2024
[c10]Jihwan Kim, Ariel Cohen, Mike Peng Li, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony:
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. CICC 2024: 1-8- 2016
- [c9]Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi:
SERDES external loopback test using production parametric-test hardware. ITC 2016: 1-7 - 2013
- [c8]Mike Peng Li, Masashi Shimanouchi, Hsinho Wu:
Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013). CICC 2013: 1-8 - [c7]Daniel Chow, Masashi Shimanouchi, Mike Peng Li:
Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities. ITC 2013: 1-8 - 2009
- [c6]Masashi Shimanouchi, Mike P. Li, Daniel Chow:
New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing. ITC 2009: 1-8 - 2004
- [c5]Masashi Shimanouchi:
Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. ITC 2004: 567-576 - [c4]A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson:
Tester Architecture For The Source Synchronous Bus. ITC 2004: 738-747 - 2003
- [c3]Masashi Shimanouchi:
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. ITC 2003: 48-57 - 2002
- [c2]Masashi Shimanouchi:
New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing. ITC 2002: 903-912 - 2001
- [c1]Masashi Shimanouchi:
An approach to consistent jitter modeling for various jitter aspects and measurement methods. ITC 2001: 848-857
Coauthor Index
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