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2000 – 2009
- 2002
[j2]Jhing-Fa Wang, Jia-Ching Wang, An-Nan Suen, Chung-Hsien Wu, Fan-Min Li:
VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(8): 1861-1869 (2002)- 2001
- [c5]Jia-Ching Wang, Jhing-Fa Wang, An-Nan Suen, Yu-Sheng Weng:
A programmable application-specific VLSI architecture for speech recognition. ICECS 2001: 477-480
1990 – 1999
- 1997
- [j1]An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin:
VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. Integr. 24(1): 79-97 (1997) - 1996
- [c4]An-Nan Suen, Jhing-Fa Wang, Bor-Yueh Liu:
A programmable application-specific CELP processor with parallel architectures. ICASSP 1996: 3252-3255 - 1995
- [c3]Jhing-Fa Wang, An-Nan Suen, Jia-Ru Lee, Chung-Hsien Wu:
A Bayesian neural network chip design for speech recognition system. ICNN 1995: 2027-2030 - [c2]An-Nan Suen, Jhing-Fa Wang, Yuen-Lin Chiang:
A Cepstrum Chip: Architecture and Implementation. ISCAS 1995: 1428-1431 - 1993
- [c1]Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu:
A High Throughput-Rate Architecture for 8*8 2-D DCT. ISCAS 1993: 1578-1590
Coauthor Index
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