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ORCIDMeng Yang 0013
Person information
- affiliation: Fudan University, ASIC and System State Key Laboratory, Shanghai, China
Other persons with the same name
- Meng Yang — disambiguation page
- Meng Yang 0001
![[0000-0002-0795-3221]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-0795-3221")
— Sun Yat-Sen University, Guangzhou, China (and 2 more) - Meng Yang 0002 — Xi'an Jiaotong University, Institute of Artificial Intelligence and Robotics, and the National Engineering Laboratory for Visual Information Processing and Applications, Xi'an, China
- Meng Yang 0003 — Hangzhou Dianzi University, College of Communication Engineering, Hangzhou, China
- Meng Yang 0004 — Nanjing University of Finance and Economics, College of Information Engineering, Nanjing, China
- Meng Yang 0005 — Shenyang Normal University, School of Mathematics and Systems Science, Shenyang, China
- Meng Yang 0006 — User Experience and Customer Insights, Burlington, MA, USA
- Meng Yang 0007 — The University of Melbourne, School of Computing and Information Systems, Melbourne, Australia
- Meng Yang 0008 — Hebei University of Science and Technology, Shijiazhuang, China
- Meng Yang 0009 — North Carolina State University, Raleigh, NC, USA
- Meng Yang 0010 — Saint Mary's University, Halifax, Canada
- Meng Yang 0011 — Beijing Forestry University, School of Information Science and Technology, Beijing, China (and 1 more)
- Meng Yang 0012 — China Ship Development and Design Center, Wuhan, China
- Meng Yang 0014 — Royal Holloway, University of London, Egham, UK
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2010 – 2019
- 2019
[c6]Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai:
An Analytical-based Hybrid Algorithm for FPGA Placement. ACM Great Lakes Symposium on VLSI 2019: 351-354- 2018
- [j5]Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai:
A SA-based parallel method for FPGA placement. IEICE Electron. Express 15(24): 20180943 (2018) - 2016
- [c5]Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai:
Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). FPGA 2016: 280 - 2014
- [j4]Meng Yang, Jinmei Lai, A. E. A. Almaini:
An Architecture Independent Packing Method for LUT-based Commercial FPGA. J. Comput. 9(5): 1131-1137 (2014) - 2013
- [j3]Meng Yang, Jiarong Tong, Jinmei Lai:
Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. J. Comput. 8(10): 2520-2526 (2013) - [j2]Meng Yang, Jinmei Lai:
Optimisation of Mixed Polarity Reed-Muller Functions. J. Softw. 8(11): 2770-2774 (2013) - [c4]Meng Yang, Jiarong Tong, A. E. A. Almaini:
Indirect connection aware attraction for FPGA clustering (abstract only). FPGA 2013: 265 - [c3]Meng Yang, Jinmei Lai, Jiarong Tong:
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. FPL 2013: 1-4 - 2011
- [c2]Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. ASICON 2011: 393-396
2000 – 2009
- 2008
- [j1]Meng Yang, Lingli Wang, Jiarong Tong, A. E. A. Almaini:
Techniques for dual forms of Reed-Muller expansion conversion. Integr. 41(1): 113-122 (2008) - 2006
- [b1]Meng Yang:
Algorithms in computer-aided design of VLSI circuits. Edinburgh Napier University, UK, 2006 - [c1]Meng Yang, Lingli Wang, A. E. A. Almaini:
Fast Conversion for Large Canonical OR-Coincidence Functions. APCCAS 2006: 1643-1646
Coauthor Index
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