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Da Li 0004
Person information
- affiliation: Beijing University of Technology, Embedded Software and Systems Institute, China
- affiliation: Xi'an Jiaotong University, School of Electronics and Information Engineering, China
Other persons with the same name
- Da Li — disambiguation page
- Da Li 0001 — Samsung AI Centre, Cambridge, UK (and 3 more)
- Da Li 0002 — Facebook Inc. (and 1 more)
- Da Li 0003 — University of Chinese Academy of Sciences (UCAS), School of Artificial Intelligence, Beijing, China (and 1 more)
- Da Li 0005 — National University of Defense Technology, School of Electronic Countermeasures, Hefei, China
- Da Li 0006 — Northwest Institute of Eco-Environment and Resources, State Key Laboratory of Cryospheric Science Lanzhou, China
- Da Li 0007 — Wuhan University of Technology, School of Information Engineering, China (and 2 more)
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2010 – 2019
- 2017
- [c3]Ting Bao, Zhangqin Huang, Da Li:
Data Loss and Reconstruction for Wireless Environmental Sensor Networks. BigDataSecurity/HPSC/IDS 2017: 48-52 - 2014
- [j4]Chunhua Xiao, Zhangqin Huang, Da Li:
A Cluster-based Hierarchical Partitioning Approach for Multiple FPGAs. J. Comput. 9(9): 2173-2180 (2014) - 2013
- [j3]Da Li, Yibin Hou, Zhangqin Huang, Chunhua Xiao:
Auto-design systematic methodology of cluster MPSoC for multiple concurrent applications. Int. J. Comput. Appl. Technol. 48(3): 253-262 (2013) - [j2]Chunhua Xiao, Zhangqin Huang, Da Li:
A Tutorial for Key Problems in the Design of Hybrid Hierarchical NoC Architectures with Wireless/RF. Smart Comput. Rev. 3(6): 425-436 (2013) - 2012
- [j1]Da Li, Yibin Hou, Zhangqin Huang, Chunhua Xiao:
Prototype Design and Synthesis of Cluster MPSoC Architecture for Multiple Applications. J. Comput. 7(11): 2671-2679 (2012) - 2011
- [c2]Da Li, Yibin Hou, Zhangqin Huang, Chunhua Xiao:
Multiprocessor System-on-Chip Design with Fuzzy Dynamic Scheduling for Parallel Video Processing. ACIS-ICIS 2011: 65-70 - [c1]Da Li, Yibin Hou, Zhangqin Huang, Chunhua Xiao:
A framework of multi-characteristics fuzzy dynamic scheduling for parallel video processing on MPSoC architecture. FUZZ-IEEE 2011: 627-634
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last updated on 2024-09-26 01:57 CEST by the dblp team
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