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2010 – 2019
- 2016
[c8]Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu:
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). ASP-DAC 2016: 139-146- [c7]Xing Wei, Yi Diao, Yu-Liang Wu:
To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. ASP-DAC 2016: 623-630 - 2015
- [c6]Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu:
A coupling area reduction technique applying ODC shifting. DATE 2015: 1461-1466 - [c5]Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu:
A universal macro block mapping scheme for arithmetic circuits. DATE 2015: 1629-1634 - 2014
- [c4]Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu:
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. ACM Great Lakes Symposium on VLSI 2014: 233-234 - [c3]Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. VLSID 2014: 375-380 - 2012
- [c2]Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. ASP-DAC 2012: 511-516 - 2011
- [c1]Yi Diao, Yu-Liang Wu:
A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions. CAD/Graphics 2011: 471-477
Coauthor Index
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