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ORCIDEnrique San Millán
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2020 – today
- 2023
[j9]Randy Lozada Dominguez
, Juan Sebastián Betancourt Perlaza, Enrique San Millán:
Time Synchronization Technique Hardware Implementation for OFDM Systems With Hermitian Symmetry for VLC Applications. IEEE Access 11: 42222-42233 (2023)- 2021
- [j8]Jose A. Belloch, Germán León, José M. Badía, Almudena Lindoso, Enrique San Millán:
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC. J. Supercomput. 77(2): 2124-2137 (2021)
2010 – 2019
- 2018
- [j7]Honorio Martín, Enrique San Millán, Luis Entrena-Arrontes:
Dynamic control of entropy and power consumption in TRNGs for IoT applications. IEICE Electron. Express 15(2): 20171157 (2018) - 2017
- [j6]Honorio Martín, Pedro Peris-López, Enrique San Millán, Juan E. Tapiador:
A lightweight implementation of the Tav-128 hash function. IEICE Electron. Express 14(11): 20161255 (2017) - 2016
- [j5]Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán:
A New TRNG Based on Coherent Sampling With Self-Timed Rings. IEEE Trans. Ind. Informatics 12(1): 91-100 (2016) - 2015
- [j4]Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter:
Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness. IEEE Trans. Inf. Forensics Secur. 10(2): 266-277 (2015) - 2014
- [j3]Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán:
An Estimator for the ASIC Footprint Area of Lightweight Cryptographic Algorithms. IEEE Trans. Ind. Informatics 10(2): 1216-1225 (2014) - [c17]Honorio Martín, Anna Vaskova, Celia López-Ongil, Enrique San Millán, Marta Portela-García:
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness. IOLTS 2014: 202-205 - 2011
- [c16]Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena:
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS 2011: 179-181 - [c15]Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez:
AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS 2011: 228-233 - 2010
- [c14]Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena:
Cryptographically secure pseudo-random bit generator for RFID tags. ICITST 2010: 1-6 - [c13]Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena:
Robust cryptographic ciphers with on-line statistical properties validation. IOLTS 2010: 208-210
2000 – 2009
- 2009
- [c12]Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena:
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS 2009: 203-205 - [c11]Pedro Peris-Lopez, Julio C. Hernandez-Castro, Juan M. Estévez-Tapiador, Enrique San Millán, Jan C. A. van der Lubbe:
Security Flaws in an Efficient Pseudo-Random Number Generator for Low-Power Environments. SEWCN 2009: 25-35 - 2008
- [c10]Enrique San Millán, Luis Entrena, José Alberto Espejo:
Logic Transformations by Multiple Wire Network Addition. DSD 2008: 779-786 - [c9]Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena:
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS 2008: 167-168 - 2007
- [j2]Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena:
Low power data processing system with self-reconfigurable architecture. J. Syst. Archit. 53(9): 568-576 (2007) - [c8]Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán:
Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721 - 2003
- [j1]Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López:
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49(12-15): 529-541 (2003) - 2001
- [c7]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472 - [c6]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397 - [c5]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299 - [c4]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94 - [c3]Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo:
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
1990 – 1999
- 1999
- [c2]Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno:
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520 - [c1]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161-
Coauthor Index
aka: Luis Entrena-Arrontes
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