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Ke Huang 0003
Person information
- affiliation: Tsinghua University, Institute of Microelectronics, Beijing, China
- affiliation (former): University of Electronic Science and Technology of China, Institute of Microelctronics, Sichuan, China
Other persons with the same name
- Ke Huang — disambiguation page
- Ke Huang 0001 — San Diego State University, Department of Electrical and Computer Engineering, CA, USA (and 3 more)
- Ke Huang 0002 — University of Electronic Science and Technology of China, School of Computer Science and Engineering, Chengdu, China (and 1 more)
- Ke Huang 0004 — University of Massachusetts, Department of Computer Science, Lowell, USA
- Ke Huang 0005 — Google, Inc., Mountain View, CA, USA (and 3 more)
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2010 – 2019
- 2015
- [j2]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1441-1450 (2015) - [c9]Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang:
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC 2015: 1-4 - [c8]Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang:
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS 2015: 1-4 - 2014
- [j1]Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang:
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 209-213 (2014) - [c7]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. CICC 2014: 1-4 - 2013
- [c6]Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 10Gb/s analog equalizer in 0.18um CMOS. ASICON 2013: 1-4 - [c5]Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang:
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. ASICON 2013: 1-4 - [c4]Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT 2013: 1-4 - 2012
- [c3]Shijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang:
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. ISCAS 2012: 309-312 - [c2]Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang:
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ISCAS 2012: 313-316 - [c1]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang:
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS 2012: 932-935
Coauthor Index
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