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Eustace Painkras
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2010 – 2019
- 2013
- [b1]Eustace Painkras:
A chip multiprocessor for a large-scale neural simulator. University of Manchester, UK, 2013 - [j5]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber:
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits 48(8): 1943-1953 (2013) - [j4]Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang:
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. 39(11): 693-708 (2013) - [j3]Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown:
Overview of the SpiNNaker System Architecture. IEEE Trans. Computers 62(12): 2454-2467 (2013) - 2012
- [j2]Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber:
Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. 72(11): 1507-1520 (2012) - [c2]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber:
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4 - 2011
- [j1]Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge:
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7(4): 17:1-17:18 (2011)
2000 – 2009
- 2008
- [c1]Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, Eustace Painkras, Stephen B. Furber:
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. IJCNN 2008: 2849-2856
Coauthor Index
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