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Hyun-chul Hwang

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2024
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  - https://dblp.org/rec/conf/vlsit/HwangKLKKK24
Hyun-chul Hwang, Min-su Kim, Daeseong Lee, Yong-geol Kim, Byung-su Kim, Kun-hyuk Kang:
An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process. VLSI Technology and Circuits 2024: 1-2

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