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ORCIDMilos Hrkic
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2000 – 2009
- 2008
[r1]Milos Hrkic, John Lillis:
Generalized Buffer Insertion. Handbook of Algorithms for Physical Design Automation 2008- 2006
- [j4]Milos Hrkic, John Lillis, Giancarlo Beraudo:
An Approach to Placement-Coupled Logic Replication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2539-2551 (2006) - [c9]Hosung (Leo) Kim, John Lillis, Milos Hrkic:
Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI 2006: 211-216 - 2004
- [j3]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 136-141 (2004) - [j2]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [c8]Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29 - [c7]Milos Hrkic, John Lillis, Giancarlo Beraudo:
An approach to placement-coupled logic replication. DAC 2004: 711-716 - [c6]Charles J. Alpert, Milos Hrkic, Stephen T. Quay:
A fast algorithm for identifying good buffer insertion candidate locations. ISPD 2004: 47-52 - 2003
- [j1]Milos Hrkic, John Lillis:
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 481-491 (2003) - [c5]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Porosity aware buffered steiner tree construction. ISPD 2003: 158-165 - 2002
- [c4]Milos Hrkic, John Lillis:
S-Tree: a technique for buffered routing tree synthesis. DAC 2002: 578-583 - [c3]Milos Hrkic, John Lillis:
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. ISPD 2002: 98-103 - [c2]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 - 2001
- [c1]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
Coauthor Index
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