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ORCIDKoichi Sasada
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2010 – 2019
- 2019
[c11]Koichi Sasada:
Gradual write-barrier insertion into a Ruby interpreter. ISMM 2019: 115-121- 2011
- [c10]Jumpei Arakawa, Koichi Sasada:
A decentralized access control mechanism using authorization certificate for distributed file systems. ICITST 2011: 148-153
2000 – 2009
- 2006
- [c9]Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915 - [c8]Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924 - 2005
- [c7]Koichi Sasada:
YARV: yet another RubyVM: innovating the ruby interpreter. OOPSLA Companion 2005: 158-159 - [c6]Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453 - [c5]Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460 - 2004
- [c4]Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323 - 2003
- [c3]Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615 - [c2]Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675 - [c1]Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
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