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Heng-Yu Jian
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2010 – 2019
- 2011
- [j4]David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Mau-Chung Frank Chang:
A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver. IEEE J. Solid State Circuits 46(7): 1606-1617 (2011) - [j3]Qun Jane Gu, Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang, Yves Baeyens, Young-Kai Chen:
CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 393-397 (2011) - 2010
- [j2]Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang:
A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator. IEEE J. Solid State Circuits 45(4): 768-780 (2010) - [c1]David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang:
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX. ESSCIRC 2010: 258-261
2000 – 2009
- 2008
- [j1]Heng-Yu Jian, Zhiwei Xu, Mau-Chung Frank Chang:
Delta-Sigma D/A Converter Using Binary- Weighted Digital-to-Analog Differentiator for Second-Order Mismatch Shaping. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 6-10 (2008)
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