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A. S. Mahadevan

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1990 – 1999

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1998
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M. Bhaskar Sherigar, A. S. Mahadevan, K. Senthil Kumar, David S. Sumam:
A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. VLSI Design 1998: 394-399

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