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2010 – 2019
- 2018
[j10]Robin Bonamy, Sébastien Bilavarn
, Fabrice Muller, François Duhem, Simon Heywood, Philippe Millet, Fabrice Lemonnier:
Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera. Int. J. Circuit Theory Appl. 46(9): 1648-1662 (2018)- 2015
- [j9]François Duhem, Fabrice Muller, Robin Bonamy, Sébastien Bilavarn:
FoRTReSS: a flow for design space exploration of partially reconfigurable systems. Des. Autom. Embed. Syst. 19(3): 301-326 (2015) - [c13]Robin Bonamy, Sébastien Bilavarn, Fabrice Muller:
An energy-aware scheduler for dynamically reconfigurable multi-core systems. ReCoSoC 2015: 1-6 - 2013
- [j8]Ikbel Belaid, Bassem Ouni, Fabrice Muller, Maher Benjemaa:
Complete and Approximate Methods for Off-Line Placement of Hardware Tasks on Reconfigurable Devices. J. Circuits Syst. Comput. 22(2) (2013) - [j7]François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini:
Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Archit. 59(8): 571-581 (2013) - [j6]François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah, Serge Weber, Philippe Lorenzini:
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. Microprocess. Microsystems 37(1): 1-8 (2013) - [j5]Clément Foucher, Fabrice Muller, Alain Giulieri:
Online codesign on reconfigurable platform for parallel computing. Microprocess. Microsystems 37(4-5): 482-493 (2013) - [j4]Clément Foucher, Fabrice Muller, Alain Giulieri:
Méthodologie dédiée aux applications parallèles sur plateforme reconfigurable dynamiquement. Tech. Sci. Informatiques 32(2): 253-280 (2013) - 2012
- [j3]François Duhem, Fabrice Muller, Philippe Lorenzini:
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. IET Comput. Digit. Tech. 6(2): 105-113 (2012) - [c12]Clément Foucher, Fabrice Muller, Alain Giulieri:
Fast integration of hardware accelerators for dynamically reconfigurable architecture. ReCoSoC 2012: 1-7 - 2011
- [b1]Fabrice Muller:
Architectures multiprocesseurs, distribuées et reconfigurables dynamiquement pour les applications temps réel. University of Nice Sophia Antipolis, France, 2011 - [j2]Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices. Int. J. Reconfigurable Comput. 2011: 591983:1-591983:28 (2011) - [c11]François Duhem, Fabrice Muller, Philippe Lorenzini:
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. ARC 2011: 253-260 - [c10]François Duhem, Fabrice Muller, Philippe Lorenzini:
Methodology for designing partially reconfigurable systems using transaction-level modeling. DASIP 2011: 316-322 - [c9]Bassem Ouni, Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Placement of Hardware Tasks on FPGA using the Bees Algorithm. PECCS 2011: 498-505 - [c8]Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Schedulers-Driven approach for dynamic placement/scheduling of multiple DAGs onto SoPCs. International Symposium on Rapid System Prototyping 2011: 179-185 - 2010
- [j1]Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA. Int. J. Reconfigurable Comput. 2010: 980762:1-980762:20 (2010) - [c7]Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
New Three-level Resource Management for Off-line Placement of Hardware Tasks on Reconfigurable Devices. ReCoSoC 2010: 29-36
2000 – 2009
- 2009
- [c6]Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Off-line placement of hardware tasks on FPGA. FPL 2009: 591-595 - 2008
- [c5]Muhammad Farooq, Fabrice Muller, Michel Auguin:
Weight Bound Limits in Supertasking Approach for Guaranteed Timeline Constraints. ICPP Workshops 2008: 9-16 - 2006
- [c4]Muhammad Farooq, Fabrice Muller, Michel Auguin:
Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks. SAC 2006: 1487-1492 - [c3]Nicole Chalhoub, Fabrice Muller, Michel Auguin:
FPGA-based generic neural network architecture. IES 2006: 1-4 - 2001
- [c2]Jacques Lonchamp, Fabrice Muller:
A Generic Support for Distributed Deliberations. HPCN Europe 2001: 221-230 - [c1]Jacques Lonchamp, Fabrice Muller:
Computer-Supported Deliberations for Distributed Teams. IICS 2001: 167-174
Coauthor Index
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