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ORCIDYeu-Horng Shiau
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2020 – today
- 2021
[j10]Yeu-Horng Shiau, Kuan-Yu Huang
, Pei-Yin Chen, Cho-Yu Kuo:
A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 677-689 (2021)
2010 – 2019
- 2019
- [j9]Yeu-Horng Shiau, Yao-Tsung Kuo, Pei-Yin Chen, Feng-Yuan Hsu:
VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications. IEEE Trans. Circuits Syst. Video Technol. 29(1): 238-251 (2019) - 2018
- [c11]Pei-Yin Chen, Yao-Tsung Kuo, Shih-Hsiang Lin, Yeu-Horng Shiau:
Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications. ISCAS 2018: 1- - 2015
- [j8]Pei-Yin Chen, Yeu-Horng Shiau, Hung-Yu Yang, Wan-Yu Jhuang:
A Weighted Edge-Preserving Smooth Filter for High Dynamic Range Image Display. J. Inf. Sci. Eng. 31(3): 1011-1026 (2015) - [j7]Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Shang-Yuan Li:
A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications. IEEE Trans. Intell. Transp. Syst. 16(2): 934-946 (2015) - 2014
- [j6]Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Chao-Ho Chen, S.-S. Wang:
Weighted haze removal method with halo prevention. J. Vis. Commun. Image Represent. 25(2): 445-453 (2014) - [c10]Yeu-Horng Shiau, Cheng-Han Li, Zhi-hao Wang, Yi Tai Guo:
Hardware and Software Co-design of the Moving Object Tracking System. IIH-MSP 2014: 305-308 - 2013
- [j5]Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Ya-Zhu Chuang:
Hardware Implementation of a Fast and Efficient Haze Removal Method. IEEE Trans. Circuits Syst. Video Technol. 23(8): 1369-1374 (2013) - 2012
- [j4]Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Shi-Gi Huang:
Power-efficient decoder implementation based on state transparent convolutional codes. IET Circuits Devices Syst. 6(4): 227-234 (2012) - [c9]Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang:
High Dynamic Range Image Rendering with Order-Statistics Filter. ICGEC 2012: 352-355 - 2011
- [c8]Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang, Ya-Zhu Chuang, Yeu-Horng Shiau:
Low Complexity Underwater Image Enhancement Based on Dark Channel Prior. IBICA 2011: 17-20
2000 – 2009
- 2009
- [j3]Pei-Yin Chen, Chien-Chuan Huang, Yeu-Horng Shiau, Yao-Tung Chen:
A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 51-55 (2009) - 2004
- [j2]Yeu-Horng Shiau, Jer-Min Jou, Chin-Chi Liu:
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme. IEICE Trans. Inf. Syst. 87-D(7): 1867-1877 (2004) - 2002
- [j1]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 924-929 (2002) - 2001
- [c7]Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang:
An efficient VLSI architecture for HMM-based speech recognition. ICECS 2001: 469-472 - [c6]Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu:
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. ISCAS (2) 2001: 529-532
1990 – 1999
- 1999
- [c5]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC 1999: 185-188 - [c4]Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang:
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. ASP-DAC 1999: 205-208 - [c3]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction. ASP-DAC 1999: 209- - [c2]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS 1999: 339-342 - [c1]Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun:
A grey prediction motion estimator for digital image processing. ICECS 1999: 701-704
Coauthor Index
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