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Burnell G. West

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2000 – 2009

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2004
[c12]
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Burnell G. West, Michael F. Jones:
Digital Synchronization for Reconfigurable ATE. ITC 2004: 1249-1254
[c11]
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Burnell G. West:
Open Architecture ATE: Prospects and Problems. ITC 2004: 1410
2003
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Burnell G. West:
Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy. ITC 2003: 947-951
[c9]
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Burnell G. West:
Multi-GB/s IC Test Challenges and Solutions. ITC 2003: 1311
2002
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Burnell G. West:
Open ATE Architecture: Key Challenges. ITC 2002: 1212-1213
2001
[c7]
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Mark Malinoski, Burnell G. West:
Rapid-response temperature control provides new defect screening opportunities. ITC 2001: 903-907
2000
[c6]
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Luca Sartori, Burnell G. West:
The path to one-picosecond accuracy. ITC 2000: 619-627

1990 – 1999

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1999
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Burnell G. West:
Accuracy requirements in at-speed functional test. ITC 1999: 780-787
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Burnell G. West:
At-speed structural test. ITC 1999: 795-800
1998
[c3]
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Burnell G. West:
Functional ATE can meet the challenges. ITC 1998: 1155
1994
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Didier Wimmers, Kris Sakaitani, Burnell G. West:
500-MHz Testing on a 100-MHz Tester. ITC 1994: 273-278

1980 – 1989

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1983
[c1]
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Burnell G. West:
Attainable Accuracy of Autocalibrating VLSI Test Systems. ITC 1983: 193-199

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