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ORCIDJorgen Peddersen
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Books and Theses
- 2008
[b1]Jorgen Peddersen:
Run-time energy-driven optimisation of embedded systems: a complete solution. University of New South Wales, Sydney, Australia, 2008
Journal Articles
- 2020
- [j4]Vikkitharan Gnanasambandapillai
, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran:
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3577-3588 (2020) - 2010
- [j3]Xin He, Jorgen Peddersen, Sri Parameswaran:
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. Des. Autom. Embed. Syst. 14(3): 231-263 (2010) - 2008
- [j2]Jorgen Peddersen, Sri Parameswaran:
Low-Impact Processor for Dynamic Runtime Power Management. IEEE Des. Test Comput. 25(1): 52-62 (2008) - [j1]Jorgen Peddersen, Sri Parameswaran:
Energy Driven Application Self-Adaptation at Run-time. J. Comput. 3(3): 14-24 (2008)
Conference and Workshop Papers
- 2015
- [c23]Josef Schneider, Jorgen Peddersen, Sri Parameswaran:
Speeding up single pass simulation of PLRUt caches. ASP-DAC 2015: 695-700 - [c22]Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran:
E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE 2015: 363-368 - [c21]Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran:
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. ICCD 2015: 216-223 - [c20]Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran:
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. ICCD 2015: 635-642 - 2014
- [c19]Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide:
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. ASP-DAC 2014: 267-273 - [c18]Josef Schneider, Jorgen Peddersen, Sri Parameswaran:
A scorchingly fast FPGA-based Precise L1 LRU cache simulator. ASP-DAC 2014: 412-417 - [c17]Josef Schneider, Jorgen Peddersen, Sri Parameswaran:
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. DAC 2014: 200:1-200:6 - 2013
- [c16]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja:
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244 - [c15]Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI 2013: 76-83 - 2012
- [c14]Liang Tang, Jorgen Peddersen, Sri Parameswaran:
A Rapid Methodology for Multi-mode Communication Circuit Generation. VLSI Design 2012: 203-208 - 2011
- [c13]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran:
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD 2011: 126-133 - [c12]Su Myat Min, Jorgen Peddersen, Sri Parameswaran:
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. VLSI Design 2011: 141-146 - 2010
- [c11]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC 2010: 356-361 - [c10]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE 2010: 496-501 - [c9]Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran:
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE 2010: 920-925 - [c8]Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC 2010: 137-144 - [c7]Xin He, Jorgen Peddersen, Sri Parameswaran:
Improved Architectures for Range Encoding in Packet Classification System. NCA 2010: 10-19 - [c6]Karin Avnit, Arcot Sowmya, Jorgen Peddersen:
ACS: Automatic Converter Synthesis for SoC Bus Protocols. TACAS 2010: 343-348 - 2009
- [c5]Xin He, Jorgen Peddersen, Sri Parameswaran:
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS 2009: 137-146 - [c4]Xin He, Jorgen Peddersen, Sri Parameswaran:
LOP_RE: Range encoding for low power packet classification. LCN 2009: 137-144 - 2007
- [c3]Jorgen Peddersen, Sri Parameswaran:
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC 2007: 890-895 - [c2]Jorgen Peddersen, Sri Parameswaran:
Energy Driven Application SelfAdaptation. VLSI Design 2007: 385-390 - 2005
- [c1]Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran:
Rapid Embedded Hardware/Software System Generation. VLSI Design 2005: 111-116
Informal and Other Publications
- 2015
- [i2]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR abs/1506.03181 (2015) - [i1]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran:
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR abs/1506.03186 (2015)
Coauthor Index
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