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ORCIDSayeeda Sultana
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2010 – 2019
- 2013
[c8]Sayeeda Sultana, Katarzyna Radecka:
Testing reversible adder/subtractor for missing control points. MWSCAS 2013: 412-415- [c7]Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka:
SAT-based reversible gate/wire replacement fault testing. MWSCAS 2013: 1075-1078 - 2011
- [c6]Sayeeda Sultana, Katarzyna Radecka, Yu Pang:
A study on relating redundancy removal in classical circuits to reversible mapping. ICCD 2011: 206-211 - [c5]Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka:
Positive Davio-based synthesis algorithm for reversible logic. ICCD 2011: 212-218 - [c4]Sayeeda Sultana, Katarzyna Radecka:
Reversible implementation of square-root circuit. ICECS 2011: 141-144 - [c3]Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka:
A novel method of synthesizing reversible logic. ISCAS 2011: 2857-2860 - [c2]Sayeeda Sultana, Katarzyna Radecka:
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL 2011: 147-152
2000 – 2009
- 2008
- [j1]Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka:
Design for Testability of QCA Logic Under Stuck-at-value Fault Model. J. Multiple Valued Log. Soft Comput. 14(1-2): 145-176 (2008) - 2006
- [c1]Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka:
Testing QCA Modular Logic. ICECS 2006: 700-703
Coauthor Index
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