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ORCIDCharles R. Moore
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2010 – 2019
- 2012
[c10]Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting microarchitectural redundancy for defect tolerance. ICCD 2012: 35-42- 2011
- [j11]Charles R. Moore:
Power efficiency as the #1 design constraint: technical perspective. Commun. ACM 54(10): 84 (2011)
2000 – 2009
- 2008
- [c9]Charles R. Moore:
Microarchitecture in the system-level integration era. MICRO 2008 - 2004
- [j10]Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode:
Scaling to the End of Silicon with EDGE Architectures. Computer 37(7): 44-55 (2004) - [j9]Charles R. Moore:
Managing the Transition from Complexity to Elegance: Design Convergence. IEEE Micro 24(1): 80 (2004) - [j8]Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High-ILP Processors. IEEE Micro 24(6): 118-127 (2004) - [j7]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore:
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Trans. Archit. Code Optim. 1(1): 62-93 (2004) - 2003
- [j6]Charles R. Moore:
Managing the Transition from Complexity to Elegance: Knowing When You Have a Problem. IEEE Micro 23(5): 88 (2003) - [j5]Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose:
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 23(6): 8-10 (2003) - [j4]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. IEEE Micro 23(6): 46-51 (2003) - [c8]Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance. ICCD 2003: 481-488 - [c7]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. ISCA 2003: 422-433 - [c6]Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Microprocessor pipeline energy analysis. ISLPED 2003: 282-287 - [c5]Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High ILP Processors. MICRO 2003: 399-410
1990 – 1999
- 1994
- [j3]Charles R. Moore, Russell C. Stanphill:
The PowerPC Alliance. Commun. ACM 37(6): 25-27 (1994) - [j2]Michael T. Vaden, Lawrence J. Merkel, Charles R. Moore, Terence M. Potter, Robert James Reese:
Design considerations for the PowerPC 601 microprocessor. IBM J. Res. Dev. 38(5): 605-620 (1994) - 1993
- [j1]Michael C. Becker, Michael S. Allen, Charles R. Moore, John S. Muhich, David P. Tuttle:
The Power PC 601 microprocessor. IEEE Micro 13(5): 54-68 (1993) - 1992
- [c4]Charles R. Moore, D. M. Balser, John S. Muhich, R. E. East:
IBM Single Chip RISC Processor (RSC). ICCD 1992: 200-204 - 1990
- [c3]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. Compcon 1990: 173-178
1980 – 1989
- 1989
- [c2]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. ICCD 1989: 138-142
1970 – 1979
- 1974
- [c1]Charles R. Moore:
Character string manipulation in APL. APL 1974: 349-353
Coauthor Index
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