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ORCIDTiberiu Chelcea
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2000 – 2009
- 2008
[c12]Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein:
Heterogeneous Latch-Based Asynchronous Pipelines. ASYNC 2008: 83-92- 2007
- [c11]Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. ASYNC 2007: 117-128 - [c10]Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, Seth Copen Goldstein:
Global Critical Path: A Tool for System-Level Timing Analysis. DAC 2007: 783-786 - [c9]Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Self-Resetting Latches for Asynchronous Micro-Pipelines. DAC 2007: 986-989 - 2006
- [j2]Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein:
Hardware compilation of application-specific memory-access interconnect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 756-771 (2006) - [c8]Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein, Mihai Budiu:
Tartan: evaluating spatial computation for whole program execution. ASPLOS 2006: 163-174 - 2005
- [c7]Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard:
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. CODES+ISSS 2005: 231-236 - 2004
- [j1]Tiberiu Chelcea, Steven M. Nowick:
Robust interfaces for mixed-timing systems. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 857-873 (2004) - [c6]Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein:
Spatial computation. ASPLOS 2004: 14-26 - 2002
- [c5]Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. DAC 2002: 405-410 - [c4]Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards:
A Burst-Mode Oriented Back-End for the Balsa Synthesis System. DATE 2002: 330-337 - [c3]Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS 2002: 355-360 - 2001
- [c2]Tiberiu Chelcea, Steven M. Nowick:
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. DAC 2001: 21-26 - 2000
- [c1]Tiberiu Chelcea, Steven M. Nowick:
Low-Latency Asynchronous FIFO's Using Token Rings. ASYNC 2000: 210-
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