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Rong Jiang 0002
Person information
- affiliation: University of Wisconsin, Electrical and Computer Engineering Department, College of Engineering, Madison, WI, USA
- affiliation: Nanjing University of Science and Technology, Department of electrical engineering, Nanjing, China
Other persons with the same name
- Rong Jiang — disambiguation page
- Rong Jiang 0001 — National University of Defense Technology, College of Computer Science and Technology, China (and 1 more)
- Rong Jiang 0003 — Tongji University, Department of Control Science and Engineering, Shanghai, China (and 2 more)
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2000 – 2009
- 2005
- [j1]Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen:
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1562-1571 (2005) - [c7]Rong Jiang, Charlie Chung-Ping Chen:
Comprehensive frequency dependent interconnect extraction and evaluation methodology. ASP-DAC 2005: 1070-1073 - [c6]Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen:
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. DAC 2005: 163-166 - [c5]Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen:
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD 2005: 683-690 - 2004
- [c4]Rong Jiang, Charlie Chung-Ping Chen:
EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. CICC 2004: 493-496 - [c3]Rong Jiang, Charlie Chung-Ping Chen:
SCORE: SPICE COmpatible Reluctance Extraction. DATE 2004: 948-953 - [c2]Rong Jiang, Charlie Chung-Ping Chen:
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. DATE 2004: 1400-1401 - 2003
- [c1]Rong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen:
PODEA: Power delivery efficient analysis with realizable model reduction. ISCAS (4) 2003: 608-611
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